1. Field of the Invention
This invention relates to a method for testing a semiconductor circuit device which ensures that an aging test of the semiconductor integrated circuit device will continue even if "latch up" occurs during the aging test, and to an apparatus for practicing the method. Also, the present invention makes it possible to inspect a semiconductor integrated circuit device with respect to liability to "latching up".
2. Description of the Related Art
In semiconductor integrated circuit devices, an abnormal increase in temperature in the package may occur due to some internal failure. There is also a risk that an abnormal increase in temperature may occur, due to some other cause, even when the semiconductor integrated circuit device is substantially free from such internal failure.
For example, in semiconductor integrated circuit devices or the like manufactured by a complementary metal oxide semiconductor (CMOS) process, there is a risk that the temperature of the package (or other portions of the device) increases due to "latch up". If "latch up" occurs in such devices, a large current flows and generates heat as Joule's heat. This increases the temperature of the package (or other portions of the device).
If an excessively high voltage is applied to an input terminal in devices having a parasitic pnpn junction, as in CMOS devices, a parasitic pnpn thyristor is turned on and an excess current flows continuously, resulting in device breakdown in some cases. This is called "latch up".
Even CMOS semiconductor integrated circuits of the same model vary in a property expressed as "liability to" or "immunity from" latch up (this property is hereinafter referred to as "latch up immunity").
In the case of devices having weak latch up immunity, there is a risk that latch up will occur even under ordinary operating conditions, in which external noise is always small. Even in devices having strong latch up immunity, latch up may occur if a large external noise is mixed in.
Conventionally, an aging test has been practiced, where a plurality of semiconductor integrated circuit devices to be tested are placed on one aging board. The plurality of devices are continuously operated by applying a power supply voltage in accordance with a rated power supply voltage of the integrated circuits. If latch up occurs in semiconductor integrated circuit devices having weak latch up immunity during such a conventional aging test, the devices are removed as defectives.
However, in this process, where those semiconductor integrated circuit devices in which latch up has occurred during an aging test are simply removed, as described above, the degree of latch up immunity of the removed semiconductor integrated circuit devices is not known. Also, when latch up occurs in a semiconductor integrated circuit device during an aging test, the semiconductor integrated circuit device is broken. Therefore, it is impossible to continue the operation test of the semiconductor integrated circuit device in which latch up has occurred during an aging test.
In some conventional methods, if latch up occurs in one of semiconductor integrated circuit devices tested by an aging test, all semiconductor integrated circuit devices in the lot containing the latched up device are thrown away. This is because the liability to latch up is latent in semiconductor integrated circuit devices and there is a risk of allowing defective devices to be sold.
For example, even if latch up occurs in only one CMOS semiconductor integrated circuit device, several hundred CMOS semiconductor integrated circuit devices in the lot containing the latched up device may be thrown away. Use of such a method imposes a large burden on manufacturing semiconductor integrated circuit devices in terms of manufacturing cost.
However, it is possible to avoid such useless disposal, if the degree of latch up immunity can be accurately determined.